Flip-chip technology is to dispose a plurality of conductive bumps or extruded electrical terminals on the bonding pads formed on the active surface of a chip, and then to flip the bumped chip onto a substrate to complete electrical connections. Comparing to the electrical connections by wire bonding, the flip chip technology provides shorter electrical connections between a chip and a substrate to enhance and achieve a higher signal transmission rate with a better signal quality for high-speed IC chips. Therefore, flip-chip technology becomes the trend for advanced semiconductor packages to provide higher operation speeds and better electrical performance. However, the flip-chip bonding between a chip and a substrate is point-to-point electrical connection. Once external stresses are encountered, the bumps will easily be broken leading to electrical connection failure between a chip and a substrate.
There are two kinds of bumps available in the market now, tin-lead solder bumps and gold bumps. However, tin-lead solder bumps can not meet the regulations of RoHS of Europe for environmental issues and the cost of gold bumps is not only high but also getting higher and higher in the recent years. Moreover, there are reliability issues if lead-free solder bumps directly replace the tin-lead solder bumps. Normally, tin-lead solder bumps need to go through reflowing processes to form tin-lead solder balls. However, during high-temperature reflowing processes, tin-lead solder bumps are melted to form solder balls leading to electrical short caused by bridging between adjacent solder balls for fine-pitch with small-spacing applications, moreover, an appropriate flip-chip gap between a bumped chip and a substrate cannot be maintained by solder balls for normal underfilling processes. On the other hand, gold bumps are jointed by high-temperature thermal compression. However, during high-temperature thermal compression processes, gold bumps will easily be crashed and deformed and an appropriate flip-chip gap between a bumped chip and a substrate cannot be maintained for normal underfilling processes in fine-pitch applications, either. Moreover, high-temperature processes will impact the functions of IC chips. Therefore, for the existing flip-chip technology either tin-lead solder bumps or gold bumps, the flip-chip gap between a bumped chip and a substrate can not effectively be controlled where the flip-chip gap will easily change due to variation of processing parameters such as temperatures or pressures causing poor underfilling qualities such as voids leading to reliability issues.
As disclosed in U.S. Pat. No. 6,229,220 by IBM, a conventional flip-chip assembly is revealed to control and maintain a uniform flip-chip gap between a bumped chip and a substrate. The cross-sectional view of the flip-chip assembly before flip-chip bonding is as shown in FIG. 1. The flip-chip assembly primarily comprises a substrate 110, a chip 120, and a plurality of copper pillars 130 on the chip 120. The substrate 110 serves as a chip carrier having a top surface 111 and a corresponding bottom surface 112 where a plurality of bump pads 114 are formed on the top surface 111. The chip 120 has a plurality of bonding pads 112 formed on the active surface 121 and is flip-chip bonded on the top surface 111 of the substrate 110 where the copper pillars 130 are disposed on the bonding pads 122 to control the flip-chip gap. A soldering material 150 is disposed on the top of each copper pillar 130. The copper pillars 130 on the chip 120 are electrically connected to the bump pads 114 and then to the internal conductive traces of the substrate 110 to an external electronic device, not shown in the figure.
As shown in FIG. 2, the soldering material 150 after reflowing processes joints the copper pillars 130 to the bump pads 114 where the heights of the copper pillars 130 are higher than the ones of the bump pads 114 and the bump pads 114 are directly exposed from the top surface 111 of the substrate 110 so that the central points 151 of the soldering material 150 cannot be disposed on an equal-dividing plane P located at the middle of the flip-chip gap H1 between the chip 120 and the substrate 110 so that the soldering material 150 is closer to the substrate 110.
As shown in FIG. 3, when the substrate 110 of the conventional flip-chip assembly mentioned above experiences warpage due to temperature differences, more thermal stresses will exert on the bump pads 114 than on the copper pillar 130 causing peeling or breaks at the solder-joint interfaces leading to electrical failure and the reliability of the flip-chip assembly is impacted. Especially, when a solder mask covers the top surface 111 of the substrate 110 to make the bump pads 114 embedded, the issues of peeling or breaks becomes serious.